This invention relates to a semiconductor integrated circuit device and also to a method of manufacturing thereof. More particularly, the present invention relates to an insulating film structure for forming a MISFET (Metal Insulator Semiconductor Field Effect Transistor) having micro-dimensions and also to a technique that can effectively be used for a process of forming such a structure.
Conventionally, the process of planarizing an insulating film formed on the gate electrode of a MISFET is carried out by means of a method of reflowing the deposited BPSG (Baron-doped Phospho Silicate Glass) film on the gate electrode at high temperature between about 85 and 90xc2x0 C. However, in the current trend of down-sizing MISFETs to micro-dimensions, while the space between the gate electrodes of two adjacently located devices becoming small, it is highly difficult to use a BPSG film as insulating film to be planarized on the gate electrode.
A so-called self align contact technique (see, inter alia, Japanese Patent Application Laid-Open No. 9-252098) is typically used for the process of connecting wires to the source/drain of a MISFET having micro-dimensions by way of a contact hole. It is a technique of forming a silicon nitride film on the upper and lateral surfaces of the gate electrode in order to produce a contact hole by utilizing the difference between the rate of etching the silicon nitride film and that of etching the insulating film that is typically made of silicon oxide and deposited on the silicon nitride film so that no margin has to be taken into consideration for the alignment of the contact hole and the gate electrode.
However, when a silicon nitride film is formed on the upper and lateral surfaces of the gate electrode of a very fine MISFET, the space between the gate electrodes of two adjacently located devices can become extremely small. Then, voids can appear in the BPSG film buried in the space. Additionally, in the case of a device to be manufactured on a design rule adapted to dimensions of 0.25 xcexcm or less, the performance of the manufactured MISFET can become degraded when a BPSG film that requires a heat treatment involving temperature above 800xc2x0 C. is applied thereto after forming the MISFET.
A Spin On Glass (SOG) film that can be obtained by applying a chemical solution of a silicon compound dissolved in an organic solvent and baking it at temperature between about 400 and 450xc2x0 C. to gasify and dispel the solvent is expected to be used as a planarized insulating film to be formed on the gate electrode of a MIS device with dimensions of 0.25 xcexcm or less requiring low process temperature because it shows an excellent gap filling effect for the space between the gate electrodes of two adjacently located devices and not costly.
Additionally, an SOG film formed by using hydrosilsesquioxan as raw material shows a low dielectric constant if compared with a silicon oxide film formed by means of CVD and hence is expected to provide an effect of reducing the wiring delay when used as interlayer insulating layer of a multilayer metal wiring system.
On the other hand, SOG film has drawbacks including (I) that it can give rise to corrosion to metal wires because it is less resistant to moisture than a CVD-silicon oxide film and (ii) that it is soft and hence can hardly withstand chemical mechanical polishing (CMP) so that, when planarizing a global region including densely wired area and scarcely wired areas, the CMP process has to be conducted after depositing a silicon oxide film on the SOG film. A variety of techniques have been proposed to bypass the drawbacks.
For instance, Japanese Patent Application Laid-Open No. 3-330982 discloses a technique of reducing the hygroscopicity of SOG film by baking the SOG film at temperature between 400 and 750xc2x0 C., subjecting it, if necessary, to an oxygen plasma processing operation (or an argon injecting operation), forming thereon an anti-moisture film (e.g., CVD-oxide film) and then thermally treating it at temperature between 550 and 750xc2x0 C.
Japanese Patent Application Laid-Open No. 8-78528 discloses a technique of preventing the aluminum (Al) wires of a device from being corroded by the gas (containing moisture) produced by the SOG film as a result of degasification by forming a through hole through the insulating film (CVD-oxide film/SOG film/CVD-oxide film) on the aluminum wire, discharging the gas by thermally treating the device at temperature between 300 and 350xc2x0 C. and subsequently forming a side wall spacer of silicon oxide film along the lateral wall of the through hole.
Japanese Patent Application Laid-Open No. 9-283515 describes a technique of suppressing micro-projections that can appear on the surface of a ceramic-like silicon oxide film when an SOG film is heat-treated in an inert gas atmosphere, the technique comprising steps of spin-coating a solution of hydrosilsesquioxan (HSQ) onto a substrate, conducting a first heat treatment process at temperature lower than 400xc2x0 C. to turn it into a pre-ceramic film and subsequently conducting a second heat treatment process at temperature lower than 400xc2x0 C. in an oxidizing gas atmosphere (oxygen+nitrogen) to produce a ceramic-like silicon oxide film.
Japanese Patent Application Laid-Open No. 8-125021 describes a technique of perfectly hardening an SOG film comprising steps of quasi-hardening the SOG film in a preliminary heat treatment process conducted at temperature between 70 and 220xc2x0 C., modifying a surface layer of the SOG film by treating it with ozone/ultraviolet rays and subsequently heat-treating it in a process conducted in an oxygen or nitrogen atmosphere and including a pre-heat-treatment at 400 to 500xc2x0 C. and a post-heat-treatment at 700 to 1,000xc2x0 C.
Finally, Japanese Patent Application Laid-Open No. 10-107026 describes a technique of improving the ant-crack performance of an SOG film made of hydrosilsesquioxan (HSQ) and raising the density thereof by curing it with electron beams at temperature between room temperature and 500xc2x0 C.
The inventors of the present invention have looked into the feasibility of using polysilazan type SOG film and hydrosilsesquioxan type SOG film for the planarized insulating film to be formed on the gate electrode of a MISFET.
Polysilazan is characterized by having a molecular structure where nitrogen (N) atoms and hydrogen (H) atoms are bonded to each silicon (Si) atom. For forming SOG film, using polysilazan as raw material, firstly a chemical solution prepared by dissolving polysilazan into a solvent is applied onto a substrate by spin coating and then the applied solution is baked to gasify and dispel the solvent. Subsequently, the SOG film is subjected to a steam-oxidation process at high temperature to make the hydrogen atoms bonded to the silicon atoms and the NH-radicals react with each other in a manner as expressed by chemical formula (1) for each molecule. Then, the produced hydrogen gas and ammonium gas are made to leave the film to produce a dense and highly moisture-resistant SOG film having Sixe2x80x94Oxe2x80x94Si bonds. 
However, the inventors of the present invention have found that the obtained SOG film contains a trace of residual nitrogen originating from polysilazan. Therefore, when an SOG film is formed on the gate electrode with a silicon nitride film interposed therebetween, it is no longer possible to secure a satisfactory level of etch selectivity necessary for forming a contact hole by utilizing the difference between the rate of etching the silicon nitride film and that of etching the SOG film particularly if the contact hole is required to have a small diameter.
On the other hand, hydrosilsesquioxan has a molecular structure where oxygen (O) atoms and hydrogen (H) atoms are bonded to each silicon (Si) atom and hence does not contain any nitrogen in the molecule. For forming SOG film, using hydrosilsesquioxan as raw material, a chemical solution prepared by dissolving hydrosilsesquioxan into a solvent is applied onto a substrate by spin coating and then the applied solution is heat-treated to gasify and dispel the solvent. As a result, a chemical reaction as expressed by formula (2) below takes place to oxidize the Sixe2x80x94H bonds by 20 to 30% and produce an SOG film having Sixe2x80x94OH bonds. 
However, since the hydrosilsesquioxan type SOG film has Sixe2x80x94H bonds in each molecule, it gives rise to a problem of producing discharging gas on hydrogen if a heat treatment is conducted at far higher temperature than 400xc2x0 C. in the process after forming the film.
For example, hydrogen gas and other gases are produced during the process of forming a through hole through the prepared hydrosilsesquioxan type SOG film and burying a conductor layer in the through hole if the temperature of forming the conductor layer exceeds 400xc2x0 C. Then, the operation of burying the conductor layer proceeds insufficiently to consequently raise the resistance of layer. Additionally, since the etching condition can become modified by the generated hydrogen gas, it is highly difficult to produce a through showing a high aspect ratio.
In view of the above identified circumstances, it is therefore an object of the present invention to provide a technique of forming an insulating film that can encourage the efforts for down-sizing MISFETs.
Other objects and novel features of the present invention will become apparent in the following description of the invention made by referring to the accompanying drawings that illustrate preferred embodiments of the invention.
Firstly, the present invention will be summarily described.
(1) A semiconductor integrated circuit device comprising: a semiconductor substrate having a principal surface; a MISFET formed on said principal surface of said semiconductor substrate; a first wiring layer formed on said MISFET with a first insulating film interposed therebetween; and a second wiring layer formed on said first wiring layer with a second insulating film interposed therebetween;
each of said first insulating film and said second insulating film including an insulating film formed by applying a liquid substance containing a polymer of silicon, oxygen and hydrogen as principal ingredient, the relative dielectric constant of said second insulating film being lower than that of said first insulating film.
(2) A semiconductor integrated circuit device as set forth in (1) above, wherein said polymer is hydrosilsesquioxan.
(3) A semiconductor integrated circuit device as set forth in (1) above, wherein the hydrogen content of said second insulating film is higher than that of said first insulating film.
(4) A semiconductor integrated circuit device as set forth in (1) above, wherein the surface of said first insulating film is planarized by polishing.
(5) A semiconductor integrated circuit device comprising: a semiconductor substrate having a principal surface, a MISFET formed on said principal surface of said semiconductor substrate; a first insulating film formed on said MISFET; a capacitive element formed on said first insulating film with a first electrode, a second electrode and a dielectric film interposed between said first and second electrodes; and a second insulating film formed on said capacitive element;
each of said first insulating film and said second insulating film including an insulating film formed by applying a liquid substance containing a polymer of silicon, oxygen and hydrogen as principal ingredient; and hydrogen content of said second insulating film being lower than that of said first insulating film.
(6) A semiconductor integrated circuit device as set forth in (5) above, wherein the relative dielectric constant of said second insulating film is higher than that of said first insulating film.
(7) A semiconductor integrated circuit device as set forth in (5) above, further comprising a first metal wire and a second metal wire formed on said capacitive element, said second insulating film being interposed between said first metal wire and said second metal wire.
(8) A semiconductor integrated circuit device comprising: a semiconductor substrate having a principal surface; a semiconductor region formed on said principal surface of said semiconductor substrate; a silicon nitride film formed on said semiconductor region; a first insulating film formed on said silicon nitride film and showing an etching rate different from said silicon nitride film; a first contact hole formed through said first insulating film and said silicon nitride film; a first conductor film formed in said first contact hole and electrically connected to said semiconductor region; and a second conductor film formed on said first insulating film with a second insulating film interposed therebetween;
said first insulating film including an insulating film formed by applying a liquid substance containing a polymer of silicon, oxygen and hydrogen as principal ingredient; and said second insulating film including an insulating film formed by applying a liquid substance containing a polymer of silicon, nitrogen and hydrogen as principal ingredient.
(9) A semiconductor integrated circuit device as set forth in (8) above, wherein said polymer of silicon, oxygen and hydrogen is hydrosilsesquioxan and said polymer of silicon, nitrogen and hydrogen is silazan.
(10) A semiconductor integrated circuit device comprising: a semiconductor substrate having a principal surface; a semiconductor region formed on said principal surface of said semiconductor substrate; a silicon nitride film formed on said semiconductor region; a first insulating film formed on said silicon nitride film and showing an etching rate different from said silicon nitride film; a first contact hole formed through said first insulating film and said silicon nitride film; and a first conductor film formed in said first contact hole and electrically connected to said semiconductor region;
said first insulating film being formed by applying a liquid substance containing a polymer of silicon, oxygen and hydrogen as principal ingredient.
(11) A semiconductor integrated circuit device comprising: a semiconductor substrate having a principal surface; a MISFET formed on said principal surface of said semiconductor substrate; a silicon nitride film formed on said MISFET; a first insulating film formed on said silicon nitride film and showing an n etching rate different from said silicon nitride film; a first contact hole formed through said first insulating film and said silicon nitride film; a first conductor film formed in said first contact hole and electrically connected to either of said source/drain of said MISFET; a capacitive element formed on said first insulating film and electrically connected to either of said source/drain by way of said first conductor film; and a first metal wire formed on said capacitive element with a second insulating film interposed therebetween;
each of said first insulating and said second insulating film including an insulating film formed by applying a liquid substance containing a polymer of silicon, oxygen and hydrogen as principal ingredient; and the relative dielectric constant of said second insulating film being lower than that of said first insulating film.
(12) A semiconductor integrated circuit device as set forth in (11), wherein the surface of said first insulating is planarized by polishing.
(13) A semiconductor integrated circuit device as set forth in (11), wherein said capacitive element comprises a capacitive insulating film, which includes a film containing high dielectrics or ferroelectrics having a perovskite crystal structure or a complex perovskite crystal structure as principal ingredient.
(14) A semiconductor integrated circuit device comprising: a semiconductor substrate having a principal surface; a MISFET formed on said principal surface of said semiconductor substrate; a silicon nitride film formed on said MISFET; a first insulating film formed on said silicon nitride film and showing an n etching rate different from said silicon nitride film; a first contact hole formed through said first insulating film and said silicon nitride film; a first conductor film formed in said first contact hole and electrically connected to either of said source/drain of said MISFET; a capacitive element formed on said first insulating film and electrically connected to either of said source/drain by way of said first conductor film; and a first metal wire formed on said capacitive element with a second insulating film interposed therebetween;
said first insulating film including an insulating film formed by applying a liquid substance containing a polymer of silicon, oxygen and hydrogen as principal ingredient, said second insulating film including an insulating film formed by applying a liquid substance containing a polymer of silicon, nitrogen and hydrogen as principal ingredient, the relative dielectric constant of said second insulating film being lower than that of said first insulating film.
(15) A semiconductor integrated circuit device comprising: a semiconductor substrate having a principal surface; a MISFET formed on said principal surface of said semiconductor substrate; a bit line formed on said MISFET with a first insulating layer interposed therebetween; a capacitive element formed on said bit line with a second insulating film interposed therebetween; and a first metal wire formed on said capacitive element with a third insulating film interposed therebetween;
said bit line being connected to either of said source/drain of said MISFET by way of a first contact hole formed through said first insulating film, said capacitive element being connected to the other of said source/drain by way of a second contact hole formed through said second insulating film and of a third contact hole formed through said first insulating film, each of said first insulating film, said second insulating film and said third insulating film including an insulating film formed by applying a liquid substance containing a polymer of silicon, oxygen and hydrogen as principal ingredient, the relative dielectric constant of said third insulating film being lower than that of said first insulating film and that of said second insulating film.
(16) A semiconductor integrated circuit device as set forth in (15), further comprising a second metal wire formed on said first metal wire with a fourth insulating film interposed therebetween, said fourth insulating film including an insulating film formed by applying a liquid substance containing a polymer of silicon, oxygen and hydrogen as principal ingredient, the relative dielectric constant of said fourth insulating being lower than that of said first insulating film and that of said second insulating film.
(17) A semiconductor integrated circuit device as set forth in (15), wherein said first insulating film comprises a silicon nitride film covering the top and lateral surfaces of the gate electrode of said MISFET and said insulating film formed on said silicon nitride film, and the surface of said first insulating film is planarized by polishing.
(18) A method of manufacturing a semiconductor integrated circuit device comprising the steps of:
(a) forming a silicon nitride film on the principal surface of a semiconductor substrate and subsequently applying a liquid substance containing a polymer of silicon, oxygen and hydrogen as principal ingredient onto said silicon nitride film;
(b) forming an insulating film by subjecting said liquid substance to a first heat treatment, thereby gasifying the solvent thereof; and
(c) forming a contact hole through said insulating and said silicon nitride film by etching said insulating with a high etching rate relative to said silicon nitride film and subsequently etching said silicon nitride film.
(19) A method of manufacturing a semiconductor integrated circuit device as set forth in (18), wherein said polymer is hydrosilsesquioxan.
(20) A method of manufacturing a semiconductor integrated circuit device as set forth in (18), wherein, after having been subjected to said first heat treatment, said insulating film is subjected to a second heat treatment at temperature higher than said first heat treatment prior to said step of etching said insulating film.
(21) A method of manufacturing a semiconductor integrated circuit device comprising steps of:
(a) forming a semiconductor region on the surface of a semiconductor substrate and subsequently applying a liquid substance containing a polymer of silicon, oxygen and hydrogen as principal ingredient onto said semiconductor region;
(b) forming an insulating film by subjecting said liquid substance to a first heat treatment, thereby gasifying the solvent thereof;
(c) subjecting said insulating film to a second heat treatment and subsequently forming a contact hole by drying etching said insulating film; and
(d) forming a conductor layer electrically connected to said semiconductor region in said contact hole.
(22) A method of manufacturing a semiconductor integrated circuit device as set forth in (21), wherein the temperature of said second heat treatment is higher than that of said first heat treatment.
(23) A method of manufacturing a semiconductor integrated circuit device comprising steps of:
(a) forming a first insulating film by applying a liquid substance containing a polymer of silicon, oxygen and hydrogen as principal ingredient onto the principal surface of a semiconductor substrate and subsequently subjecting said liquid substance to a first heat treatment, thereby gasifying the solvent thereof;
(b) subjecting said first insulating film to a second heat treatment in an oxygen-containing atmosphere and subsequently chemically and mechanically polishing the surface of said first insulating film;
(c) forming a conductor member by forming a conductor film on said first insulating film and subsequently by etching said conductor film; and
(d) forming a second insulating film on said conductor member.
(24) A method of manufacturing a semiconductor integrated circuit device as set forth in (23), wherein the relative dielectric constant of said second insulating film is lower than that of said first insulating film.
(25) A method of manufacturing a semiconductor integrated circuit device as set forth in (23), wherein the hydrogen content of said second insulating film is higher than that of said first insulating film.
(26) A method of manufacturing a semiconductor integrated circuit device as set forth in (23), wherein said second insulating film is formed by applying a liquid substance containing a polymer of silicon, oxygen and hydrogen as principal ingredient onto said conductor member and subsequently by subjecting said liquid substance to a first heat treatment, thereby gasifying the solvent thereof.
(27) A method of manufacturing a semiconductor integrated circuit device comprising steps of:
(a) forming a plurality of first conductor members on the principal surface of a semiconductor substrate and subsequently applying a liquid substance containing a polymer of silicon, oxygen and hydrogen as principal ingredient into a space between said first conductor members and also onto said first conductor members;
(b) forming an insulating film by subjecting said liquid substance to a first heat treatment, thereby gasifying the solvent thereof, and subsequently subjecting it to a second heat treatment in an oxygen-containing atmosphere;
(c) forming a capacitive element including a first electrode, a capacitive insulating film and a second electrode on said insulating film.
(28) A method of manufacturing a semiconductor integrated circuit device as set forth in (27), wherein the temperature of said second heat treatment is higher than that of said first heat treatment.
(29) A method of manufacturing a semiconductor integrated circuit device as set forth in (27), wherein the temperature of said second heat treatment is higher than the temperature for forming said capacitive insulating film of said capacitive element.
(30) A method of manufacturing a semiconductor integrated circuit device as set forth in (27), wherein said capacitive insulating film of said capacitive element includes a film containing high dielectrics or ferroelectrics having a perovskite crystal structure or a complex perovskite crystal structure as principal ingredient.
(31) A method of manufacturing a semiconductor integrated circuit device comprising steps of:
(a) forming a plurality of first conductor members on the principal surface of a semiconductor substrate and subsequently applying a first liquid substance containing a polymer of silicon, oxygen and hydrogen as principal ingredient into a space between said first conductor members and also onto said first conductor members;
(b) forming a first insulating film by subjecting said liquid substance to a first heat treatment, thereby gasifying the solvent thereof, and subsequently subjecting it to a second heat treatment in an oxygen-containing atmosphere;
(c) forming a capacitive element including a first electrode, a capacitive insulating film and a second electrode on said first insulating film and subsequently applying a second liquid substance containing a polymer of silicon, oxygen and hydrogen as principal ingredient onto said capacitive element;
(d) forming a second insulating film by subjecting said second liquid substance to a third heat treatment, thereby gasifying the solvent thereof.
(32) A method of manufacturing a semiconductor integrated circuit device as set forth in (31), wherein said polymer is hydrosilsesquioxan.
(33) A method of manufacturing a semiconductor integrated circuit device as set forth in (31), wherein the temperature of said second heat treatment is higher than that of said first heat treatment and that of said third heat treatment.
(34) A method of manufacturing a semiconductor integrated circuit device as set forth in (31), wherein the temperature of said second heat treatment is higher than the temperature for forming said capacitive insulating film of said capacitive element.
(35) A method of manufacturing a semiconductor integrated circuit device as set forth in (31), wherein the relative dielectric constant of said second insulating film is lower than that of said first insulating film.
(36) A method of manufacturing a semiconductor integrated circuit device as set forth in (31), wherein said step of forming said capacitive element on said first insulating film includes a step of forming a third insulating film on said first insulating film by CVD, a step of forming a groove in said third insulating film and a step of forming said capacitive element in said groove.
(37) A method of manufacturing a semiconductor integrated circuit device comprising a step of forming a MISFET on the principal surface of a semiconductor substrate and subsequently forming a first insulating film on said MISFET and a step of forming a capacitive element including a first electrode, a capacitive insulating film and a second electrode on said first insulating film and subsequently forming a second insulating film on said capacitive element; each of said first insulating and said second insulating film including an insulating film formed by applying a liquid substance containing a polymer of silicon, oxygen and hydrogen as principal ingredient; and the relative dielectric constant of said second insulating film being lower than that of said first insulating film.
(38) A method of manufacturing a semiconductor integrated circuit device as set forth in (37), wherein the surface of said first insulating film is planarized by chemical and mechanical polishing.
(39) A method of manufacturing a semiconductor integrated circuit device as set forth in (37), wherein the hydrogen content of said second insulating film is higher than that of said first insulating film.
(40) A method of manufacturing a semiconductor integrated circuit device as set forth in (37), further comprising a step of forming a first metal wire on said second insulating film and forming a second metal wire on said first metal wire with a third insulating film interposed therebetween, said third insulating film including an insulating film formed by applying a liquid substance containing a polymer of silicon, oxygen and hydrogen as principal ingredient, the relative dielectric constant of said third insulating film being lower than that of said first insulating film.
(41) A method of manufacturing a semiconductor integrated circuit device comprising steps of:
(a) forming a MISFET on the principal surface of a semiconductor substrate and subsequently applying a first liquid substance containing a polymer of silicon, oxygen and hydrogen as principal ingredient;
(b) forming a first insulating film by subjecting said first liquid substance to a first heat treatment and subsequently subjecting said first insulating film to a second heat treatment to be conducted at temperature higher than said first heat treatment in an oxygen-containing atmosphere;
(c) forming a metal wire containing aluminum (Al) as principal ingredient on said first insulating film and subsequently applying a second liquid substance containing a polymer of silicon, oxygen and hydrogen as principal ingredient onto said metal wire; and
(d) forming a second insulating film by subjecting said second liquid substance to a third heat treatment to be conducted at temperature lower than said second heat treatment.
(42) A method of manufacturing a semiconductor integrated circuit device as set forth in (41), wherein the relative dielectric constant of said second insulating film is lower than that of said first insulating film.
(43) A method of manufacturing a semiconductor integrated circuit device as set forth in (41), wherein the temperature of said third heat treatment is lower than that of degrading said metal wire.
(44) A method of manufacturing a semiconductor integrated circuit device as set forth in (41), further comprising a step of planarizing the surface of said first insulating film by chemical and mechanical polishing to be conducted after said step (b).
(45) A method of manufacturing a semiconductor integrated circuit device as set forth in (41), further comprising:
(e) a step of irradiating ultraviolet rays to the surface of said second insulating film in an oxygen-containing atmosphere to be conducted after said step (d);
(f) a step of applying a third liquid substance containing a polymer of silicon, oxygen and hydrogen as principal ingredient to the surface of said second insulating film irradiated with ultraviolet rays; and
(g) a step of raising the height of said second insulating film by subjecting said third liquid substance to a fourth heat treatment.
(46) A method of manufacturing a semiconductor integrated circuit device comprising steps of:
(a) forming a MISFET on the principal surface of a semiconductor substrate and subsequently applying a first liquid substance containing a polymer of silicon, oxygen and hydrogen as principal ingredient onto said MISFET;
(b) forming a first insulating film by subjecting said first liquid substance to a first heat treatment and subsequently subjecting said first insulating film to a second heat treatment to be conducted at temperature higher than said first heat treatment in an oxygen-containing atmosphere;
(c) forming a capacitive element on said first insulating film and subsequently applying a second liquid substance containing a polymer of silicon, oxygen and hydrogen as principal ingredient onto said capacitive element; and
(d) forming a second insulating film by subjecting said second liquid substance to a third heat treatment to be conducted at temperature lower than said second heat treatment.
(47) A method of manufacturing a semiconductor integrated circuit device as set forth in (46), wherein the temperature of said third heat treatment is lower than that of degrading said capacitive insulating film of said capacitive element.
(48) A method of manufacturing a semiconductor integrated circuit device comprising steps of:
(a) forming a groove on the element isolating region of the principal surface of a semiconductor substrate and subsequently applying liquid substance containing a polymer of silicon, oxygen and hydrogen as principal ingredient onto said semiconductor substrate including the inside portion of said groove;
(b) forming an insulating film by subjecting said liquid substance to a first heat treatment and subsequently subjecting said insulating film to a second heat treatment to be conducted at temperature higher than said first heat treatment in an oxygen-containing atmosphere; and
(c) forming an element isolating groove on the principal surface of said semiconductor substrate by chemically and mechanically polishing said insulating film subjected to said second heat treatment, leaving said insulating film in the inside portion of said groove.
(49) A method of manufacturing a semiconductor integrated circuit device as set forth in (48), wherein said polymer is hydrosilsesquioxan.
According to the invention, it is now possible to realize a self align contact with ease because an insulating film showing a high etching rate relative to a silicon nitride film can be prepared by forming said insulating film on a MISFET, using a polymer not containing nitrogen as raw material.
According to the invention, it is now possible to use a CMP technique to an insulating film formed by applying a polymer substance because the density of the formed film can be raised by subjecting it to a heat treatment at high temperature.
According to the invention, the inter-wire parasitic capacitance can be reduced by using an insulating film showing a low dielectric constant for the interlayer insulating film to be arranged between wires.
According to the invention, it is now possible to reduce the cost of manufacturing a semiconductor integrated circuit device by using an insulating film formed by applying a polymer substance that is less expensive than an insulating film formed by CVD.
According to the invention, it is now possible to obtain an insulating film practically not containing hydrogen by subjecting a film formed by applying a polymer substance to a heat treatment at high temperature. Therefore, it is possible to effectively prevent the insulating film from discharging gas.